(a) Field
Embodiments of the present invention relate to a clock signal generating circuit and a power supply including the same.
(b) Description of the Related Art
A frequency synthesizer for changing a frequency of an input signal into a predetermined output frequency and outputting the same uses a phase locked loop.
FIG. 1 shows a frequency synthesizer using a conventional phase locked loop.
As shown in FIG. 1, the frequency synthesizer 1 includes a phase detector 2, a pulse-voltage converter 3, a voltage controlled oscillator 4, and a divider 5.
The voltage controlled oscillator 4 generates an output signal having a frequency following an input voltage. The divider 5 divides the output signal and feeds it back to the phase detector 2 so as to change the output frequency into a frequency of the input signal.
The phase detector 2 compares the fed output signal and the input signal and generates a pulse signal according to a phase difference between the two signals.
The pulse-voltage converter 3 controls the voltage that is input to the voltage controlled oscillator 4 according to the pulse signal to control the frequency of the output signal to be equal to the output frequency.
The pulse-voltage converter 3 includes a charge pump and a loop filter, and the loop filter includes a capacitor that is charged and discharged by charges transmitted by the charge pump or charges transmitted to the charge pump.
In this instance, as the frequency of the input signal becomes lower, the size of the capacitor of the loop filter is problematically increased. That is, the conventional frequency synthesizer requires a large capacitor so as to change the frequency of the input signal in a slow frequency bandwidth into the output frequency. When the capacitor is large, it is impossible to integrate it with the semiconductor technology.
In order to solve this, a digital phase locked loop can be used. However, this method requires several periods of the input signal in order to lock the phase, and the several periods amount to a very long time when the frequency of the input signal is low.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.